Design of arithmetic and logic unit (ALU)

ALU role and datapath signals

Definition. An arithmetic and logic unit performs selected operations on input operands and produces a result plus status information. Control signals select operations such as add, subtract, AND, OR, XOR, compare, or shift. The ALU is part of a datapath; registers, buses, multiplexers, and control logic supply operands and use its result.

Example. An ALU may choose $A+B$ when opcode is 000 and $A\land B$ when opcode is 010.

Exam point. Operation code determines function; operand width and signedness determine interpretation.

Bitwise logic operations

Definition. Bitwise AND, OR, XOR, and NOT apply Boolean operations independently at each bit position. They do not propagate carries. For an $n$-bit word, each output has the same width, with any unused high bits governed by the operation's definition.

Example. $1010\land1100=1000$.

Exam point. Distinguish bitwise logic from logical truth-value operations on an entire word.

Solved calculation. Compute AND, OR, and XOR of $A=101101$ and $B=110011$.

1. AND each bit: 100001.
2. OR each bit: 111111.
3. XOR each bit: 011110.
4. The results are six bits because both operands are six bits. Answer. AND=100001, OR=111111, XOR=011110.

Binary addition in an ALU

Definition. An $n$-bit adder adds two bit vectors and a carry-in. Each bit uses propagate/generate behavior; sum is XOR of the operands and carry-in. The low $n$ result bits are retained, while carry-out and signed overflow are separate status conditions.

Example. Four-bit $1111+0001=1,0000$, yielding result 0000 and carry-out 1.

Exam point. Report the result width and flags independently.

Solved calculation. Add unsigned 8-bit values 01101101 and 00111011.

1. From the least significant end: 1+1=0, carry 1.
2. Next bit: 0+1+1=0, carry 1.
3. Continue full addition: $01101101+00111011=10101000$.
4. The operands sum to 168, which fits in 8 unsigned bits, so carry-out is 0. Answer. 10101000, carry-out 0.

Full-adder equations

Definition. A full adder computes $S_i=A_i\oplus B_i\oplus C_i$ and $C_{i+1}=A_iB_i+(A_i\oplus B_i)C_i$. Equivalently, carry-out is the majority of $A_i,B_i,C_i$. Cascading full adders forms a ripple-carry adder.

Example. For inputs 1,0,1, sum is 0 and carry is 1.

Exam point. Carry is generated by both operand bits or propagated from the prior position.

Solved calculation. Find sum and carry for bit inputs $A_i=1,B_i=1,C_i=0$.

1. $S=1\oplus1\oplus0=0$.
2. $G=A_iB_i=1$.
3. $P=A_i\oplus B_i=0$.
4. $C_{i+1}=G+PC_i=1$. Answer. Sum 0, carry-out 1.

Ripple-carry adder

Definition. A ripple-carry adder connects each stage's carry-out to the next stage's carry-in. Its area is approximately linear in bit width for a fixed gate implementation, but the worst-case carry delay also grows with width. It is simple and appropriate when timing requirements allow the propagation delay.

Example. A 4-bit ripple adder uses four carry stages to form a 4-bit sum and final carry.

Exam point. The longest carry chain determines the worst-case delay, not a typical input pattern.

Solved calculation. An 8-bit ripple adder has 2 ns carry delay per stage. Estimate worst-case carry-out delay when eight stages are serial.

1. Carry must pass through eight stages in the simplified model.
2. Delay is $8\times2=16$ ns.
3. This omits input arrival and sum-generation delay, which are not specified. Answer. 16 ns under the stated model.

Carry propagate and generate

Definition. Define $G_i=A_iB_i$ and $P_i=A_i\oplus B_i$. Then $C_{i+1}=G_i+P_iC_i$. A group of bits can compute whether it generates a carry independently of the input carry and whether it propagates a carry through the group, enabling faster lookahead structures.

Example. $G_i=1$ forces carry-out to 1 even when carry-in is 0.

Exam point. Some texts define propagate as $A_i+B_i$; state the convention and use it consistently.

Solved calculation. For two low bits, let $(G_0,P_0)=(0,1)$ and $(G_1,P_1)=(1,0)$ with $C_0=1$.

1. $C_1=G_0+P_0C_0=0+1=1$.
2. $C_2=G_1+P_1C_1=1+0=1$.
3. The high bit generates carry regardless of C1. Answer. $C_2=1$.