I/O interface (interrupt and DMA)

I/O subsystem and device interface

Definition. An I/O subsystem connects the processor and memory to peripheral devices with different speeds, data formats, and control requirements. A device controller exposes data, status, and control registers. The interface may use memory-mapped or isolated I/O addressing, depending on the ISA and system design.

Example. A keyboard controller sets a status bit when a character is available.

Exam point. Distinguish the peripheral from its controller and register interface.

Memory-mapped I/O

Definition. Memory-mapped I/O assigns device registers addresses in the processor's memory address space. Ordinary load/store instructions access those registers, but the addresses may have side effects and often require uncached or ordered accesses. The usable address space is shared with memory.

Example. A store to a control-register address may start a disk operation.

Exam point. A read from a device register may clear a status bit or consume data; it is not always a passive memory read.

Isolated I/O

Definition. Isolated or port-mapped I/O uses a separate address space and special input/output instructions. It can preserve memory addresses for RAM and ROM, but requires distinct instruction and control paths. Whether a system uses this mode is an architectural choice.

Example. An IN instruction may read a byte from I/O port 0x60.

Exam point. Port addresses and memory addresses are not interchangeable in an isolated-I/O design.

Polling

Definition. In programmed I/O with polling, the processor repeatedly reads a device status register and transfers data when the ready condition appears. Polling is simple and can be efficient for frequent events when the processor has little other work, but it wastes cycles when the device is slow or idle.

Example. The CPU checks a printer-ready bit until it becomes 1.

Exam point. Polling latency depends on check interval; CPU time is consumed while waiting.

Solved calculation. A processor checks status every 200 cycles. A device becomes ready just after a check. What is the worst polling detection delay, ignoring read time?

1. Readiness just after a check waits almost one full interval.
2. The next check occurs 200 cycles later.
3. The worst-case delay approaches 200 cycles; the average under uniform arrival is about 100 cycles. Answer. Worst case is nearly 200 cycles; average is 100 cycles under uniform timing.

Interrupt-driven I/O

Definition. With interrupt-driven I/O, a device signals the processor when service is needed. The processor completes or pauses current work, saves required state, executes an interrupt handler, services the device, and resumes. Interrupts reduce busy waiting but incur entry, context, and service overhead.

Example. A network controller interrupts when a packet buffer is ready.

Exam point. Interrupts are asynchronous events relative to the instruction stream, though handling is coordinated by hardware.

Interrupt request and service sequence

Definition. A typical interrupt sequence detects a request, checks priority and masking, finishes or suspends an instruction, saves architectural state, identifies the source, transfers control to a handler, services the device, acknowledges the request, restores state, and returns. Exact ordering varies by architecture and interrupt type.

Example. A maskable interrupt may remain pending while interrupts are disabled.

Exam point. Distinguish interrupt acknowledgment from device data transfer.

Solved example. A timer interrupt arrives while a program is running. Name the essential actions before normal execution resumes.

1. The processor recognizes the request at an allowed boundary.
2. It saves the return PC and any state required by the calling convention or hardware.
3. It selects the timer handler, directly or through a vector.
4. The handler records the event and acknowledges or clears the timer request.
5. State is restored and return transfers control to the saved PC. Answer. Save context, dispatch, service/acknowledge, restore, and return.