Instruction set and addressing modes

Instruction set architecture

Definition. An instruction set architecture (ISA) defines the machine-visible behavior of a processor. It specifies operations, registers, data types, instruction formats, addressing modes, and how control transfers. The ISA is the contract between software and an implementation; microarchitecture determines how the contract is carried out.

Example. Two processors may execute the same ISA while using different pipeline depths and cache designs.

Exam point. Separate architectural behavior from internal implementation choices.

Instruction fields and formats

Definition. An instruction is encoded as fields such as opcode, register identifiers, immediate constants, and addressing-mode bits. A fixed-length format keeps instruction boundaries simple, while variable-length formats can improve code density but complicate decoding. Field widths determine how many operations, registers, or immediate values can be represented.

Example. A 32-bit instruction with a 6-bit opcode leaves 26 bits for operands and other fields.

Exam point. Sum field widths and check whether the resulting encoding fits the instruction length.

Solved calculation. A 32-bit instruction has a 6-bit opcode, two 5-bit register fields, and a 16-bit immediate. How many bits remain?

1. Used bits are $6+5+5+16=32$.
2. No bits remain for separate addressing-mode flags.
3. If the design needs extra fields, it must reuse bits or provide another format. Answer. 0 bits remain.

Zero-, one-, two-, and three-address instructions

Definition. An instruction's address count is the number of explicit operand addresses encoded, not necessarily the number of values it uses. A three-address operation names two sources and a destination; two-address forms often overwrite one source. Accumulator and stack machines may omit operands because the location is implied.

Example. ADD R1,R2,R3 may mean $R1\leftarrow R2+R3$; a two-address ADD R1,R2 may mean $R1\leftarrow R1+R2$.

Exam point. Read the operand order and destination convention before tracing a sequence.

Solved example. Evaluate $X=(A+B)(C+D)$ on a two-address machine where MUL X,Y means $X\leftarrow X\times Y$.

1. Compute $A+B$ into temporary $T_1$.
2. Compute $C+D$ into $T_2$.
3. Multiply $T_1$ by $T_2$, overwriting $T_1$.
4. Move the result to X if the multiply destination cannot be chosen as X. Answer. A valid sequence is MOV T1,A; ADD T1,B; MOV T2,C; ADD T2,D; MUL T1,T2; MOV X,T1.

Register and memory operands

Definition. A register operand is held in a processor register; a memory operand is fetched from an address. Register-register instructions use registers for arithmetic, while load-store ISAs perform arithmetic only on registers and use separate load/store operations. Memory-memory instructions can name memory locations directly but may need more complex execution.

Example. LOAD R1,[A] fetches the word at address A; ADD R1,R2 operates on registers.

Exam point. Count memory references from explicit loads, stores, and instruction fetches only when the question asks for them.

Immediate addressing

Definition. In immediate addressing, a constant is encoded in the instruction itself. It avoids a separate data-memory read for that operand, but the value range is limited by the immediate field width and its extension rule. Signed immediates are commonly sign-extended; unsigned immediates are zero-extended.

Example. ADD R1,R2,#7 computes $R1\leftarrow R2+7$.

Exam point. Determine whether an immediate is signed and how many bits it occupies.

Solved calculation. A 6-bit two's-complement immediate field contains 111101. Find its value after sign extension to 16 bits.

1. The sign bit is 1, so the 6-bit value is negative.
2. Invert and add one: 000010+1=000011, giving magnitude 3.
3. Its value is −3.
4. Sign extension fills the upper ten bits with 1: 1111111111111101. Answer. −3; extended pattern 1111111111111101.

Direct and absolute addressing

Definition. In direct or absolute addressing, the instruction contains the effective memory address or a field directly interpreted as that address. The operand is read from that location. The maximum addressable range depends on address-field width and whether the address is byte- or word-based.

Example. LOAD R0,[0x120] reads from address 0x120.

Exam point. The address field is not the operand value; it identifies where the operand is stored.

Register-indirect addressing

Definition. Register-indirect mode uses a register whose contents are the effective address. The register may be called a pointer or base register. This mode supports arrays, pointers, and dynamic data structures without placing a full address in every instruction.

Example. If R4 contains 1000, LOAD R1,[R4] reads from memory address 1000.

Exam point. Distinguish the register number from the address stored inside that register.

Solved calculation. R2 contains 240 and memory word M[240] contains 17. What does LOAD R5,[R2] do?

1. Register-indirect mode uses the contents of R2 as the effective address.
2. Effective address is 240.
3. The word at M[240], namely 17, is copied to R5. Answer. R5 becomes 17; R2 remains 240 unless the instruction specifies update.