Design of control unit: hardwired and microprogrammed

Control unit and control signals

Definition. A control unit issues signals that coordinate datapath operations, memory transfers, and instruction sequencing. It interprets the current instruction and relevant status conditions, then selects the actions required in each clock step. Control signals may be combinational or stored as part of a control state.

Example. A register-load enable causes a register to capture its input at the active clock edge.

Exam point. Distinguish a control signal's asserted meaning from its electrical polarity.

Instruction execution phases

Definition. A typical instruction passes through fetch, decode, operand access, execute, and write-back activities, though implementations combine or split them differently. Fetch obtains instruction bits and advances or updates the PC. Decode identifies the operation and determines which resources are needed.

Example. A register add may fetch/decode, read operands, add, then write the result.

Exam point. A phase list is conceptual; do not assume every instruction uses every phase.

Solved trace. Outline control actions for LOAD R1,[R2+8] in a simple multi-cycle datapath.

1. Fetch: memory address receives PC; instruction register loads returned instruction; PC advances.
2. Decode: control identifies LOAD, reads R2, and sign-extends displacement 8.
3. Address calculation: ALU adds R2 and displacement.
4. Memory access: effective address drives data memory read.
5. Write-back: memory data is selected and written into R1. Answer. Five conceptual steps; actual hardware may combine some steps.

Hardwired control

Definition. Hardwired control generates control outputs using logic gates, decoders, state registers, and timing signals. Its behavior is fixed by circuit structure. It can be fast for a fixed ISA but may be difficult to modify when the instruction set or control sequence changes.

Example. Opcode bits feed a decoder whose output enables the ALU's add operation.

Exam point. “Hardwired” describes implementation, not whether a processor has a control state machine.

Microprogrammed control

Definition. A microprogrammed control unit stores control words in a control memory. Each microinstruction asserts a set of microoperations and determines the next microinstruction address, either sequentially or through a branch condition. Changing control behavior can be easier than rewiring a large control network, but control-memory access adds design constraints.

Example. A microinstruction can simultaneously read a register, select an ALU function, and load a destination register if those operations are compatible.

Exam point. A microinstruction is an internal control step; it is not necessarily a machine-level instruction.

Microoperations and control words

Definition. A microoperation is an elementary register transfer or datapath action completed in a control step. A control word encodes which microoperations occur and may include source selection, ALU function, destination enables, memory control, and next-address information. Simultaneous operations must not demand conflicting resources.

Example. MAR←PC, PC←PC+4 can occur together if address and increment paths support both values.

Exam point. Check resource conflicts before combining microoperations into one control word.

Solved example. Can R1←R2 and R1←R3 occur in one control step on a datapath with one write port?

1. Both operations require a write to the same register R1.
2. They request different source values at the same time.
3. One write port can accept only one selected value per step. Answer. No; they conflict. Schedule them in separate steps or add appropriate hardware.

Control memory and microprogram counter

Definition. The control address register or microprogram counter (µPC) selects a microinstruction. A next-address field may select the next sequential word, jump to a routine, dispatch based on opcode, or branch on a status condition. The control store contains the microprogram and may be writable or fixed.

Example. A conditional microbranch chooses address 24 if Z=1 and address 25 otherwise.

Exam point. Separate the current microinstruction address from the next-address decision.

Solved calculation. A control store has 256 words, each 40 bits. Find address width and capacity.

1. 256 locations require $\log_2 256=8$ address bits.
2. Capacity is $256\times40=10240$ bits.
3. In bytes this is 1280 bytes, ignoring implementation overhead. Answer. 8 address bits; 10,240 bits or 1,280 bytes.